1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming MIS (Metal-Insulator-Semiconductor) contact structures on transistor devices in CMOS applications and the resulting transistor devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. Irrespective of the physical configuration of the transistor device, each device comprises source and drain (S/D) regions and a gate electrode structure positioned above and between the S/D regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
Irrespective of whether a planar or non-planar device is considered, electrical connections must be formed to the device so that it may operate as intended. That is, electrical connections must be made to the source region, the drain region and the gate electrode of the device. Typically, the conductive contact structures that actually make contact with the device itself, i.e., the source region, the drain region and the gate electrode, are referred to as “contacts” within the industry. Such conductive contacts are formed in one or more layers of insulating material. The entire arrangement of the conductive contacts and the associated layer(s) of insulating material are sometimes referred to as the “contact level” of the overall electrical “wiring arrangement” that is formed to provide electrical connection to the integrated circuit device.
Historically, the formation of conductive contact structures to the source/drain (S/D) regions of a field effect transistor includes the formation of a metal silicide material on the S/D regions of the device. Such metal silicide regions are typically formed in the S/D regions so as to reduce the electrical resistance between the conductive contact structure and the S/D regions. Such metal silicide regions may be made using a variety of different refractory metals, e.g., nickel, platinum, titanium, cobalt, etc., including combinations of such materials, and they may be formed using techniques that are well known to those skilled in the art. One illustrative prior art process flow that was performed to form such metal silicide regions within a contact opening or a trench included the following: (1) depositing a layer of insulating material above the device including the S/D regions; (2) forming contact openings in the layer of insulating material so as to expose a portion of the S/D regions; (3) depositing a layer of refractory metal (e.g., Ni, NiPt) within the contact openings and on and in contact with the exposed portions of the S/D regions; (4) forming a capping layer (e.g., TiN) on the layer of refractory metal; (5) performing an initial heating process causing the refractory metal to react with underlying silicon-containing material in the S/D regions and form an initial form of the metal silicide material that has a relatively high electrical resistance; (6) performing an etching process to remove unreacted portions of the layer of refractory metal; (7) performing an additional heating process to form a final, lower resistance phase of the metal silicide material; and (8) performing an additional stripping process to remove any unreacted materials. Another prior art metal silicide formation technique involves (1) formation of a layer of refractory metal (e.g., Ti) on the S/D region; (2) depositing a capping layer (e.g., TiN) on the layer of refractory metal; and (3) performing an RTA laser-based anneal process.
However, as device technology continues to advance, the above-described formation of metal silicide regions as part of the conductive S/D contact structures has become more problematic for several reasons. For example, advanced devices (both planar and FinFET devices) may be manufactured using materials other than traditional silicon, such as, for example, silicon germanium, germanium, III-V materials, which may suffer from higher S/D contact resistance as compared to traditional silicon-based devices. Additionally, the ongoing decrease in device dimensions has also mandated an associated decrease in physical size of the contact openings and the conductive S/D contact structures that are formed to establish electrical connections to, for example, the S/D regions. The formation of the initial lower-resistance phase metal silicide material in such reduced-size contact openings can be difficult. Moreover, to convert the initial relatively higher resistance form of the metal silicide material into the more desirable lower resistance phase of the metal silicide material requires performing an additional heating process that reduces the overall thermal budget available for forming the entire device, and, in some cases, may lead to the formation of non-continuous layers of metal silicide regions and/or agglomeration of the metal silicide material.
With respect to some particular metal silicide materials, certain particularized problems may arise. For example, with respect to titanium silicide (TiSi), an interfacial oxide material tends to form between the titanium silicide and the underlying substrate material, thereby increasing contact resistance which leads to a reduction in device performance. In the case of other silicide materials, such as nickel silicide (NiSi) or nickel platinum silicide (NiPtSi), the metal silicide material may diffuse or form in undesired locations on the device, i.e., the silicide material may encroach toward the gate structure. Such undesired encroachment by such metal silicide materials can lead to electrical shorts, increase leakage currents, etc., all of which may lead to device and yield degradation. Cobalt di-silicide materials (CoSi2) are difficult to reliably form on substrate materials that comprise germanium, such as silicon germanium (Si(1-x)Gex), because germanium is soluble in cobalt mono-silicide (CoSi) and immiscible in cobalt di-silicide (CoSi2), which results in the movement of germanium away from the SiGe lattice and leads to agglomeration, which increases the contact resistance and reduces channel mobility. Lastly, attempts to implant relatively large ions (e.g., arsenic (As), antimony (Sb) and selenium (Se)) into the underlying epi material in a source/drain region and/or within the metal silicide material leads to processing complexity and may lead to the reducing of desirable stress profiles, e.g., tensile or compressive, in the epi and channel region of the device, which can reduce device performance.
Device designers have explored using different contact methods and structures to improve the operational characteristics of the devices and/or to simplify processing techniques. For example, U.S. Pat. No. 8,110,887 is an example of an MIS (Metal-Insulator-Semiconductor) contact structure for transistor devices. However, what is needed for modern, high packing density applications is a method of forming MIS contact structures that is more efficient and effective in terms of its use of space and the formation of a lower resistance structure for various transistor devices.
The present disclosure is directed to various methods of forming MIS contact structures on transistor devices in CMOS applications and the resulting transistor devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.